/***************************************************************************//**
* \file cyip_flashc.h
*
* \brief
* FLASHC IP definitions
*
********************************************************************************
* \copyright
* (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
*     http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/

#ifndef _CYIP_FLASHC_H_
#define _CYIP_FLASHC_H_

#include "cyip_headers.h"

/*******************************************************************************
*                                    FLASHC
*******************************************************************************/

#define FLASHC_MPC_SECTION_SIZE                 0x00001000UL
#define FLASHC_FM_CTL_SECTION_SIZE              0x00001000UL
#define FLASHC_SECTION_SIZE                     0x00010000UL

/**
  * \brief MPC Memory Protection Controller registers (FLASHC_MPC)
  */
typedef struct {
  __IOM uint32_t CFG;                           /*!< 0x00000000 Config register with error response, RegionID PPC_MPC_MAIN is
                                                                the security owner PC. The error response configuration is
                                                                located in CFG.RESPONSE, only one such configuration exists
                                                                applying to all protection contexts in the system. */
   __IM uint32_t RESERVED[63];
  __IOM uint32_t CTRL;                          /*!< 0x00000100 Control register with lock bit and auto-increment only
                                                                (Separate CTRL for each PC depends on access_pc) */
   __IM uint32_t BLK_MAX;                       /*!< 0x00000104 Max value of block-based index register */
   __IM uint32_t BLK_CFG;                       /*!< 0x00000108 Block size & initialization in progress */
  __IOM uint32_t BLK_IDX;                       /*!< 0x0000010C Index of 32-block group accessed through BLK_LUT (Separate IDX
                                                                for each PC depending on access_pc) */
  __IOM uint32_t BLK_LUT;                       /*!< 0x00000110 NS status for 32 blocks at BLK_IDX with PC=<access_pc> */
   __IM uint32_t RESERVED1[59];
  __IOM uint32_t ROT_CTRL;                      /*!< 0x00000200 Control register with lock bit and auto-increment only */
   __IM uint32_t RESERVED2;
   __IM uint32_t ROT_BLK_MAX;                   /*!< 0x00000208 Max value of block-based index register for ROT */
   __IM uint32_t ROT_BLK_CFG;                   /*!< 0x0000020C Same as BLK_CFG */
  __IOM uint32_t ROT_BLK_IDX;                   /*!< 0x00000210 Index of 8-block group accessed through ROT_BLK_LUT_* */
  __IOM uint32_t ROT_BLK_PC;                    /*!< 0x00000214 Protection context of 8-block group accesses through
                                                                ROT_BLK_LUT */
  __IOM uint32_t ROT_BLK_LUT;                   /*!< 0x00000218 (R,W,NS) bits for 8 blocks at ROT_BLK_IDX for PC=ROT_BKL_PC */
   __IM uint32_t RESERVED3[889];
} FLASHC_MPC_Type;                              /*!< Size = 4096 (0x1000) */

/**
  * \brief Flash Macro Registers are maintained by SONOS FM team. Please read 002-26677 BROS for details. (FLASHC_FM_CTL)
  */
typedef struct {
   __IM uint32_t RESERVED[16];
  __IOM uint32_t RED_CTL01;                     /*!< 0x00000040 Redundancy Control normal sectors 0,1 */
  __IOM uint32_t RED_CTL23;                     /*!< 0x00000044 Redundancy Control normal sectors 2,3 */
   __IM uint32_t RESERVED1[494];
  __IOM uint32_t FM_PL_DATA[132];               /*!< 0x00000800 Flash macro Page Latches data */
  __IOM uint32_t FLASH_MACRO_CTL;               /*!< 0x00000A10 Flash macro control */
   __IM uint32_t STATUS;                        /*!< 0x00000A14 Status */
  __IOM uint32_t FM_ADDR;                       /*!< 0x00000A18 Flash macro address */
  __IOM uint32_t BOOKMARK;                      /*!< 0x00000A1C Bookmark register - keeps the current FW HV seq */
   __IM uint32_t GEOMETRY;                      /*!< 0x00000A20 Regular flash geometry */
   __IM uint32_t GEOMETRY_SUPERVISORY;          /*!< 0x00000A24 Supervisory flash geometry */
  __IOM uint32_t ANA_CTL0;                      /*!< 0x00000A28 Analog control 0 */
  __IOM uint32_t ANA_CTL1;                      /*!< 0x00000A2C Analog control 1 */
  __IOM uint32_t FM_PL_WRDATA_ALL;              /*!< 0x00000A30 Flash macro write page latches all */
  __IOM uint32_t FM_REFRESH_ADDR;               /*!< 0x00000A34 Address bit to point to scratch area */
  __IOM uint32_t RGRANT_DELAY_ERS;              /*!< 0x00000A38 R-grant delay for erase */
  __IOM uint32_t RGRANT_SCALE_ERS;              /*!< 0x00000A3C R-grant delay scale for erase */
  __IOM uint32_t PW_SEQ23;                      /*!< 0x00000A40 HV Pulse Delay for seq2 post & seq3 */
  __IOM uint32_t PW_SEQ12;                      /*!< 0x00000A44 HV Pulse Delay for seq 1&2 pre */
  __IOM uint32_t WAIT_CTL;                      /*!< 0x00000A48 Wait State control */
  __IOM uint32_t RGRANT_DELAY_PRG;              /*!< 0x00000A4C R-grant delay for program */
  __IOM uint32_t TIMER_CLK_CTL;                 /*!< 0x00000A50 Timer prescaler (clk_t to timer clock frequency divider) */
  __IOM uint32_t TIMER_CTL;                     /*!< 0x00000A54 Timer control */
   __OM uint32_t ACLK_CTL;                      /*!< 0x00000A58 MPCON clock */
  __IOM uint32_t INTR;                          /*!< 0x00000A5C Interrupt */
  __IOM uint32_t INTR_SET;                      /*!< 0x00000A60 Interrupt set */
  __IOM uint32_t INTR_MASK;                     /*!< 0x00000A64 Interrupt mask */
   __IM uint32_t INTR_MASKED;                   /*!< 0x00000A68 Interrupt masked */
  __IOM uint32_t CAL_CTL0;                      /*!< 0x00000A6C Cal control - VCT, VBG, CDAC, IPREF */
  __IOM uint32_t CAL_CTL1;                      /*!< 0x00000A70 Cal control - ICREF, IPREF */
  __IOM uint32_t CAL_CTL2;                      /*!< 0x00000A74 Cal control - IDAC, IBS_CTL, LAT_DIS */
  __IOM uint32_t CAL_CTL3;                      /*!< 0x00000A78 Cal control - OSC trims, FDIV, REG_ACT, TURBO, LP_ULP_SW */
  __IOM uint32_t CAL_CTL4;                      /*!< 0x00000A7C Cal control - VLIM, IDAC, SDAC, ITIM ULP trims */
  __IOM uint32_t CAL_CTL5;                      /*!< 0x00000A80 Cal control - VLIM, IDAC, SDAC, ITIM LP trims */
  __IOM uint32_t CAL_CTL6;                      /*!< 0x00000A84 Cal control - SA CTL LP/ULP trims */
  __IOM uint32_t CAL_CTL7;                      /*!< 0x00000A88 Cal control - ERSX8_CLK_SEL, FM_ACTIVE, TURBO_EXT */
   __IM uint32_t RESERVED2[29];
  __IOM uint32_t FM_PL_ECC[33];                 /*!< 0x00000B00 Flash macro Page Latches ECC */
   __IM uint32_t RESERVED3[31];
   __IM uint32_t FM_MEM_DATA[132];              /*!< 0x00000C00 Flash macro memory sense amplifier data */
   __IM uint32_t RESERVED4[60];
   __IM uint32_t FM_MEM_ECC[33];                /*!< 0x00000F00 Flash macro memory sense amplifier ECC. */
   __IM uint32_t RESERVED5[26];
   __IM uint32_t FM_ECC_CTL_ADDR;               /*!< 0x00000FEC Internal ECC signal - unused */
   __IM uint32_t FM_RED_CTL_SM01_ADDR;          /*!< 0x00000FF0 0 */
   __IM uint32_t FM_RED_CTL67_ADDR;             /*!< 0x00000FF4 0 */
   __IM uint32_t FM_RED_CTL45_ADDR;             /*!< 0x00000FF8 0 */
   __IM uint32_t FM_CAL_CTL8_ADDR;              /*!< 0x00000FFC 0 */
} FLASHC_FM_CTL_Type;                           /*!< Size = 4096 (0x1000) */

/**
  * \brief FLASHC (FLASHC)
  */
typedef struct {
  __IOM uint32_t FLASH_CTL;                     /*!< 0x00000000 Flash control */
   __IM uint32_t RESERVED[64];
   __IM uint32_t FLASH_SECTOR_M;                /*!< 0x00000104 # of sector of a FM */
   __IM uint32_t FLASH_MAIN_N;                  /*!< 0x00000108 Size of MAIN in 8KB block for each pair of sectors */
   __IM uint32_t FLASH_WORK_Z;                  /*!< 0x0000010C Size of WORK in 8KB block for each pair of sectors */
   __IM uint32_t FLASH_SFLASH_Y;                /*!< 0x00000110 Size of SLFASH in 8KB block in Sector 1 */
   __IM uint32_t FLASH_REFRESH_ROW;             /*!< 0x00000114 Size of refresh rows for each sector */
   __IM uint32_t RESERVED1[58];
  __IOM uint32_t FLASH_CMD;                     /*!< 0x00000200 Command */
  __IOM uint32_t FLASH_LOCK;                    /*!< 0x00000204 Flash Controller Lock Register */
  __IOM uint32_t FLASH_PWR_CTL;                 /*!< 0x00000208 Flash power control */
   __IM uint32_t ENFORCE_PC_LOCK_SHADOW;        /*!< 0x0000020C Shadow bit of FLASH_CTL.ENFORCE_PC_LOCK */
   __IM uint32_t RESERVED2[380];
  __IOM uint32_t ECC_INJ_EN;                    /*!< 0x00000800 ECC injection enable on read */
  __IOM uint32_t ECC_INJ_CTL;                   /*!< 0x00000804 ECC injection control */
  __IOM uint32_t ECC_LOGIR;                     /*!< 0x00000808 Interrupt threshold for number of ECC correctable error */
   __IM uint32_t RESERVED3[509];
        FLASHC_MPC_Type MPC[1];                 /*!< 0x00001000 MPC Memory Protection Controller registers */
        FLASHC_FM_CTL_Type FM_CTL;              /*!< 0x00002000 Flash Macro Registers are maintained by SONOS FM team. Please
                                                                read 002-26677 BROS for details. */
} FLASHC_Type;                                  /*!< Size = 12288 (0x3000) */


/* FLASHC_MPC.CFG */
#define FLASHC_MPC_CFG_RESPONSE_Pos             4UL
#define FLASHC_MPC_CFG_RESPONSE_Msk             0x10UL
/* FLASHC_MPC.CTRL */
#define FLASHC_MPC_CTRL_AUTO_INC_Pos            8UL
#define FLASHC_MPC_CTRL_AUTO_INC_Msk            0x100UL
#define FLASHC_MPC_CTRL_LOCK_Pos                31UL
#define FLASHC_MPC_CTRL_LOCK_Msk                0x80000000UL
/* FLASHC_MPC.BLK_MAX */
#define FLASHC_MPC_BLK_MAX_VALUE_Pos            0UL
#define FLASHC_MPC_BLK_MAX_VALUE_Msk            0xFFFFFFFFUL
/* FLASHC_MPC.BLK_CFG */
#define FLASHC_MPC_BLK_CFG_BLOCK_SIZE_Pos       0UL
#define FLASHC_MPC_BLK_CFG_BLOCK_SIZE_Msk       0xFUL
#define FLASHC_MPC_BLK_CFG_INIT_IN_PROGRESS_Pos 31UL
#define FLASHC_MPC_BLK_CFG_INIT_IN_PROGRESS_Msk 0x80000000UL
/* FLASHC_MPC.BLK_IDX */
#define FLASHC_MPC_BLK_IDX_VALUE_Pos            0UL
#define FLASHC_MPC_BLK_IDX_VALUE_Msk            0xFFFFFFFFUL
/* FLASHC_MPC.BLK_LUT */
#define FLASHC_MPC_BLK_LUT_ATTR_NS0_Pos         0UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS0_Msk         0x1UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS1_Pos         1UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS1_Msk         0x2UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS2_Pos         2UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS2_Msk         0x4UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS3_Pos         3UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS3_Msk         0x8UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS4_Pos         4UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS4_Msk         0x10UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS5_Pos         5UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS5_Msk         0x20UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS6_Pos         6UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS6_Msk         0x40UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS7_Pos         7UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS7_Msk         0x80UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS8_Pos         8UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS8_Msk         0x100UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS9_Pos         9UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS9_Msk         0x200UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS10_Pos        10UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS10_Msk        0x400UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS11_Pos        11UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS11_Msk        0x800UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS12_Pos        12UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS12_Msk        0x1000UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS13_Pos        13UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS13_Msk        0x2000UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS14_Pos        14UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS14_Msk        0x4000UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS15_Pos        15UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS15_Msk        0x8000UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS16_Pos        16UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS16_Msk        0x10000UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS17_Pos        17UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS17_Msk        0x20000UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS18_Pos        18UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS18_Msk        0x40000UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS19_Pos        19UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS19_Msk        0x80000UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS20_Pos        20UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS20_Msk        0x100000UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS21_Pos        21UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS21_Msk        0x200000UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS22_Pos        22UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS22_Msk        0x400000UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS23_Pos        23UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS23_Msk        0x800000UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS24_Pos        24UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS24_Msk        0x1000000UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS25_Pos        25UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS25_Msk        0x2000000UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS26_Pos        26UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS26_Msk        0x4000000UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS27_Pos        27UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS27_Msk        0x8000000UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS28_Pos        28UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS28_Msk        0x10000000UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS29_Pos        29UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS29_Msk        0x20000000UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS30_Pos        30UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS30_Msk        0x40000000UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS31_Pos        31UL
#define FLASHC_MPC_BLK_LUT_ATTR_NS31_Msk        0x80000000UL
/* FLASHC_MPC.ROT_CTRL */
#define FLASHC_MPC_ROT_CTRL_AUTO_INC_Pos        8UL
#define FLASHC_MPC_ROT_CTRL_AUTO_INC_Msk        0x100UL
#define FLASHC_MPC_ROT_CTRL_LOCK_Pos            31UL
#define FLASHC_MPC_ROT_CTRL_LOCK_Msk            0x80000000UL
/* FLASHC_MPC.ROT_BLK_MAX */
#define FLASHC_MPC_ROT_BLK_MAX_VALUE_Pos        0UL
#define FLASHC_MPC_ROT_BLK_MAX_VALUE_Msk        0xFFFFFFFFUL
/* FLASHC_MPC.ROT_BLK_CFG */
#define FLASHC_MPC_ROT_BLK_CFG_BLOCK_SIZE_Pos   0UL
#define FLASHC_MPC_ROT_BLK_CFG_BLOCK_SIZE_Msk   0xFUL
#define FLASHC_MPC_ROT_BLK_CFG_INIT_IN_PROGRESS_Pos 31UL
#define FLASHC_MPC_ROT_BLK_CFG_INIT_IN_PROGRESS_Msk 0x80000000UL
/* FLASHC_MPC.ROT_BLK_IDX */
#define FLASHC_MPC_ROT_BLK_IDX_VALUE_Pos        0UL
#define FLASHC_MPC_ROT_BLK_IDX_VALUE_Msk        0xFFFFFFFFUL
/* FLASHC_MPC.ROT_BLK_PC */
#define FLASHC_MPC_ROT_BLK_PC_PC_Pos            0UL
#define FLASHC_MPC_ROT_BLK_PC_PC_Msk            0xFUL
/* FLASHC_MPC.ROT_BLK_LUT */
#define FLASHC_MPC_ROT_BLK_LUT_ATTR0_Pos        0UL
#define FLASHC_MPC_ROT_BLK_LUT_ATTR0_Msk        0x7UL
#define FLASHC_MPC_ROT_BLK_LUT_ATTR1_Pos        4UL
#define FLASHC_MPC_ROT_BLK_LUT_ATTR1_Msk        0x70UL
#define FLASHC_MPC_ROT_BLK_LUT_ATTR2_Pos        8UL
#define FLASHC_MPC_ROT_BLK_LUT_ATTR2_Msk        0x700UL
#define FLASHC_MPC_ROT_BLK_LUT_ATTR3_Pos        12UL
#define FLASHC_MPC_ROT_BLK_LUT_ATTR3_Msk        0x7000UL
#define FLASHC_MPC_ROT_BLK_LUT_ATTR4_Pos        16UL
#define FLASHC_MPC_ROT_BLK_LUT_ATTR4_Msk        0x70000UL
#define FLASHC_MPC_ROT_BLK_LUT_ATTR5_Pos        20UL
#define FLASHC_MPC_ROT_BLK_LUT_ATTR5_Msk        0x700000UL
#define FLASHC_MPC_ROT_BLK_LUT_ATTR6_Pos        24UL
#define FLASHC_MPC_ROT_BLK_LUT_ATTR6_Msk        0x7000000UL
#define FLASHC_MPC_ROT_BLK_LUT_ATTR7_Pos        28UL
#define FLASHC_MPC_ROT_BLK_LUT_ATTR7_Msk        0x70000000UL


/* FLASHC_FM_CTL.RED_CTL01 */
#define FLASHC_FM_CTL_RED_CTL01_RED_ADDR_0_Pos  0UL
#define FLASHC_FM_CTL_RED_CTL01_RED_ADDR_0_Msk  0xFFUL
#define FLASHC_FM_CTL_RED_CTL01_RED_EN_0_Pos    8UL
#define FLASHC_FM_CTL_RED_CTL01_RED_EN_0_Msk    0x100UL
#define FLASHC_FM_CTL_RED_CTL01_RED_ADDR_1_Pos  16UL
#define FLASHC_FM_CTL_RED_CTL01_RED_ADDR_1_Msk  0xFF0000UL
#define FLASHC_FM_CTL_RED_CTL01_RED_EN_1_Pos    24UL
#define FLASHC_FM_CTL_RED_CTL01_RED_EN_1_Msk    0x1000000UL
#define FLASHC_FM_CTL_RED_CTL01_RED_AXA_Pos     25UL
#define FLASHC_FM_CTL_RED_CTL01_RED_AXA_Msk     0x2000000UL
/* FLASHC_FM_CTL.RED_CTL23 */
#define FLASHC_FM_CTL_RED_CTL23_RED_ADDR_2_Pos  0UL
#define FLASHC_FM_CTL_RED_CTL23_RED_ADDR_2_Msk  0xFFUL
#define FLASHC_FM_CTL_RED_CTL23_RED_EN_2_Pos    8UL
#define FLASHC_FM_CTL_RED_CTL23_RED_EN_2_Msk    0x100UL
#define FLASHC_FM_CTL_RED_CTL23_RED_ADDR_3_Pos  16UL
#define FLASHC_FM_CTL_RED_CTL23_RED_ADDR_3_Msk  0xFF0000UL
#define FLASHC_FM_CTL_RED_CTL23_RED_EN_3_Pos    24UL
#define FLASHC_FM_CTL_RED_CTL23_RED_EN_3_Msk    0x1000000UL
/* FLASHC_FM_CTL.FM_PL_DATA */
#define FLASHC_FM_CTL_FM_PL_DATA_DATA32_Pos     0UL
#define FLASHC_FM_CTL_FM_PL_DATA_DATA32_Msk     0xFFFFFFFFUL
/* FLASHC_FM_CTL.FLASH_MACRO_CTL */
#define FLASHC_FM_CTL_FLASH_MACRO_CTL_FM_MODE_Pos 0UL
#define FLASHC_FM_CTL_FLASH_MACRO_CTL_FM_MODE_Msk 0xFUL
#define FLASHC_FM_CTL_FLASH_MACRO_CTL_FM_SEQ_Pos 8UL
#define FLASHC_FM_CTL_FLASH_MACRO_CTL_FM_SEQ_Msk 0x300UL
#define FLASHC_FM_CTL_FLASH_MACRO_CTL_DAA_MUX_SEL_Pos 16UL
#define FLASHC_FM_CTL_FLASH_MACRO_CTL_DAA_MUX_SEL_Msk 0xFF0000UL
#define FLASHC_FM_CTL_FLASH_MACRO_CTL_IF_SEL_Pos 24UL
#define FLASHC_FM_CTL_FLASH_MACRO_CTL_IF_SEL_Msk 0x1000000UL
#define FLASHC_FM_CTL_FLASH_MACRO_CTL_WR_EN_Pos 25UL
#define FLASHC_FM_CTL_FLASH_MACRO_CTL_WR_EN_Msk 0x2000000UL
/* FLASHC_FM_CTL.STATUS */
#define FLASHC_FM_CTL_STATUS_TIMER_STATUS_Pos   0UL
#define FLASHC_FM_CTL_STATUS_TIMER_STATUS_Msk   0x1UL
#define FLASHC_FM_CTL_STATUS_HV_REGS_ISOLATED_Pos 1UL
#define FLASHC_FM_CTL_STATUS_HV_REGS_ISOLATED_Msk 0x2UL
#define FLASHC_FM_CTL_STATUS_ILLEGAL_HVOP_Pos   2UL
#define FLASHC_FM_CTL_STATUS_ILLEGAL_HVOP_Msk   0x4UL
#define FLASHC_FM_CTL_STATUS_TURBO_N_Pos        3UL
#define FLASHC_FM_CTL_STATUS_TURBO_N_Msk        0x8UL
#define FLASHC_FM_CTL_STATUS_WR_EN_MON_Pos      4UL
#define FLASHC_FM_CTL_STATUS_WR_EN_MON_Msk      0x10UL
#define FLASHC_FM_CTL_STATUS_IF_SEL_MON_Pos     5UL
#define FLASHC_FM_CTL_STATUS_IF_SEL_MON_Msk     0x20UL
#define FLASHC_FM_CTL_STATUS_TIMER_PE_SYNC_Pos  6UL
#define FLASHC_FM_CTL_STATUS_TIMER_PE_SYNC_Msk  0x40UL
#define FLASHC_FM_CTL_STATUS_R_GRANT_DELAY_STATUS_Pos 7UL
#define FLASHC_FM_CTL_STATUS_R_GRANT_DELAY_STATUS_Msk 0x80UL
#define FLASHC_FM_CTL_STATUS_FM_BUSY_Pos        8UL
#define FLASHC_FM_CTL_STATUS_FM_BUSY_Msk        0x100UL
#define FLASHC_FM_CTL_STATUS_FM_READY_Pos       9UL
#define FLASHC_FM_CTL_STATUS_FM_READY_Msk       0x200UL
#define FLASHC_FM_CTL_STATUS_POS_PUMP_VLO_Pos   10UL
#define FLASHC_FM_CTL_STATUS_POS_PUMP_VLO_Msk   0x400UL
#define FLASHC_FM_CTL_STATUS_NEG_PUMP_VHI_Pos   11UL
#define FLASHC_FM_CTL_STATUS_NEG_PUMP_VHI_Msk   0x800UL
#define FLASHC_FM_CTL_STATUS_RWW_Pos            12UL
#define FLASHC_FM_CTL_STATUS_RWW_Msk            0x1000UL
#define FLASHC_FM_CTL_STATUS_ECC_CFG_Pos        13UL
#define FLASHC_FM_CTL_STATUS_ECC_CFG_Msk        0x2000UL
#define FLASHC_FM_CTL_STATUS_SECTOR1_SR_Pos     14UL
#define FLASHC_FM_CTL_STATUS_SECTOR1_SR_Msk     0x4000UL
#define FLASHC_FM_CTL_STATUS_RESET_MM_Pos       15UL
#define FLASHC_FM_CTL_STATUS_RESET_MM_Msk       0x8000UL
#define FLASHC_FM_CTL_STATUS_ROW_ODD_Pos        16UL
#define FLASHC_FM_CTL_STATUS_ROW_ODD_Msk        0x10000UL
#define FLASHC_FM_CTL_STATUS_ROW_EVEN_Pos       17UL
#define FLASHC_FM_CTL_STATUS_ROW_EVEN_Msk       0x20000UL
#define FLASHC_FM_CTL_STATUS_HVOP_SUB_SECTOR_N_Pos 18UL
#define FLASHC_FM_CTL_STATUS_HVOP_SUB_SECTOR_N_Msk 0x40000UL
#define FLASHC_FM_CTL_STATUS_HVOP_SECTOR_Pos    19UL
#define FLASHC_FM_CTL_STATUS_HVOP_SECTOR_Msk    0x80000UL
#define FLASHC_FM_CTL_STATUS_HVOP_BULK_ALL_Pos  20UL
#define FLASHC_FM_CTL_STATUS_HVOP_BULK_ALL_Msk  0x100000UL
#define FLASHC_FM_CTL_STATUS_CBUS_RA_MATCH_Pos  21UL
#define FLASHC_FM_CTL_STATUS_CBUS_RA_MATCH_Msk  0x200000UL
#define FLASHC_FM_CTL_STATUS_CBUS_RED_ROW_EN_Pos 22UL
#define FLASHC_FM_CTL_STATUS_CBUS_RED_ROW_EN_Msk 0x400000UL
#define FLASHC_FM_CTL_STATUS_RQ_ERROR_Pos       23UL
#define FLASHC_FM_CTL_STATUS_RQ_ERROR_Msk       0x800000UL
#define FLASHC_FM_CTL_STATUS_PUMP_PDAC_Pos      24UL
#define FLASHC_FM_CTL_STATUS_PUMP_PDAC_Msk      0xF000000UL
#define FLASHC_FM_CTL_STATUS_PUMP_NDAC_Pos      28UL
#define FLASHC_FM_CTL_STATUS_PUMP_NDAC_Msk      0xF0000000UL
/* FLASHC_FM_CTL.FM_ADDR */
#define FLASHC_FM_CTL_FM_ADDR_RA_Pos            0UL
#define FLASHC_FM_CTL_FM_ADDR_RA_Msk            0xFFFFUL
#define FLASHC_FM_CTL_FM_ADDR_BA_Pos            16UL
#define FLASHC_FM_CTL_FM_ADDR_BA_Msk            0xFF0000UL
#define FLASHC_FM_CTL_FM_ADDR_AXA_Pos           24UL
#define FLASHC_FM_CTL_FM_ADDR_AXA_Msk           0x1000000UL
/* FLASHC_FM_CTL.BOOKMARK */
#define FLASHC_FM_CTL_BOOKMARK_BOOKMARK_Pos     0UL
#define FLASHC_FM_CTL_BOOKMARK_BOOKMARK_Msk     0xFFFFFFFFUL
/* FLASHC_FM_CTL.GEOMETRY */
#define FLASHC_FM_CTL_GEOMETRY_ROW_COUNT_Pos    0UL
#define FLASHC_FM_CTL_GEOMETRY_ROW_COUNT_Msk    0xFFFFUL
#define FLASHC_FM_CTL_GEOMETRY_BANK_COUNT_Pos   16UL
#define FLASHC_FM_CTL_GEOMETRY_BANK_COUNT_Msk   0xFF0000UL
#define FLASHC_FM_CTL_GEOMETRY_WORD_SIZE_LOG2_Pos 24UL
#define FLASHC_FM_CTL_GEOMETRY_WORD_SIZE_LOG2_Msk 0xF000000UL
#define FLASHC_FM_CTL_GEOMETRY_PAGE_SIZE_LOG2_Pos 28UL
#define FLASHC_FM_CTL_GEOMETRY_PAGE_SIZE_LOG2_Msk 0xF0000000UL
/* FLASHC_FM_CTL.GEOMETRY_SUPERVISORY */
#define FLASHC_FM_CTL_GEOMETRY_SUPERVISORY_ROW_COUNT_Pos 0UL
#define FLASHC_FM_CTL_GEOMETRY_SUPERVISORY_ROW_COUNT_Msk 0xFFFFUL
#define FLASHC_FM_CTL_GEOMETRY_SUPERVISORY_BANK_COUNT_Pos 16UL
#define FLASHC_FM_CTL_GEOMETRY_SUPERVISORY_BANK_COUNT_Msk 0xFF0000UL
#define FLASHC_FM_CTL_GEOMETRY_SUPERVISORY_WORD_SIZE_LOG2_Pos 24UL
#define FLASHC_FM_CTL_GEOMETRY_SUPERVISORY_WORD_SIZE_LOG2_Msk 0xF000000UL
#define FLASHC_FM_CTL_GEOMETRY_SUPERVISORY_PAGE_SIZE_LOG2_Pos 28UL
#define FLASHC_FM_CTL_GEOMETRY_SUPERVISORY_PAGE_SIZE_LOG2_Msk 0xF0000000UL
/* FLASHC_FM_CTL.ANA_CTL0 */
#define FLASHC_FM_CTL_ANA_CTL0_MDAC_Pos         0UL
#define FLASHC_FM_CTL_ANA_CTL0_MDAC_Msk         0x7FUL
#define FLASHC_FM_CTL_ANA_CTL0_SPARE_ANA_CTL0_Pos 7UL
#define FLASHC_FM_CTL_ANA_CTL0_SPARE_ANA_CTL0_Msk 0x80UL
#define FLASHC_FM_CTL_ANA_CTL0_ECC_ENC_DIS_Pos  8UL
#define FLASHC_FM_CTL_ANA_CTL0_ECC_ENC_DIS_Msk  0x100UL
#define FLASHC_FM_CTL_ANA_CTL0_DNU_2_TM_ECC_DIS_Pos 9UL
#define FLASHC_FM_CTL_ANA_CTL0_DNU_2_TM_ECC_DIS_Msk 0x200UL
#define FLASHC_FM_CTL_ANA_CTL0_RST_SFT_HVPL_Pos 10UL
#define FLASHC_FM_CTL_ANA_CTL0_RST_SFT_HVPL_Msk 0x400UL
#define FLASHC_FM_CTL_ANA_CTL0_FLIP_AMUXBUS_AB_Pos 11UL
#define FLASHC_FM_CTL_ANA_CTL0_FLIP_AMUXBUS_AB_Msk 0x800UL
#define FLASHC_FM_CTL_ANA_CTL0_NDAC_MIN_Pos     12UL
#define FLASHC_FM_CTL_ANA_CTL0_NDAC_MIN_Msk     0xF000UL
#define FLASHC_FM_CTL_ANA_CTL0_PDAC_MIN_Pos     16UL
#define FLASHC_FM_CTL_ANA_CTL0_PDAC_MIN_Msk     0xF0000UL
#define FLASHC_FM_CTL_ANA_CTL0_SCALE_PRG_SEQ01_Pos 20UL
#define FLASHC_FM_CTL_ANA_CTL0_SCALE_PRG_SEQ01_Msk 0x300000UL
#define FLASHC_FM_CTL_ANA_CTL0_SCALE_PRG_SEQ12_Pos 22UL
#define FLASHC_FM_CTL_ANA_CTL0_SCALE_PRG_SEQ12_Msk 0xC00000UL
#define FLASHC_FM_CTL_ANA_CTL0_SCALE_PRG_SEQ23_Pos 24UL
#define FLASHC_FM_CTL_ANA_CTL0_SCALE_PRG_SEQ23_Msk 0x3000000UL
#define FLASHC_FM_CTL_ANA_CTL0_SCALE_SEQ30_Pos  26UL
#define FLASHC_FM_CTL_ANA_CTL0_SCALE_SEQ30_Msk  0xC000000UL
#define FLASHC_FM_CTL_ANA_CTL0_SCALE_PRG_PEON_Pos 28UL
#define FLASHC_FM_CTL_ANA_CTL0_SCALE_PRG_PEON_Msk 0x30000000UL
#define FLASHC_FM_CTL_ANA_CTL0_SCALE_PRG_PEOFF_Pos 30UL
#define FLASHC_FM_CTL_ANA_CTL0_SCALE_PRG_PEOFF_Msk 0xC0000000UL
/* FLASHC_FM_CTL.ANA_CTL1 */
#define FLASHC_FM_CTL_ANA_CTL1_NDAC_MAX_Pos     0UL
#define FLASHC_FM_CTL_ANA_CTL1_NDAC_MAX_Msk     0xFUL
#define FLASHC_FM_CTL_ANA_CTL1_NDAC_STEP_Pos    4UL
#define FLASHC_FM_CTL_ANA_CTL1_NDAC_STEP_Msk    0xF0UL
#define FLASHC_FM_CTL_ANA_CTL1_PDAC_MAX_Pos     8UL
#define FLASHC_FM_CTL_ANA_CTL1_PDAC_MAX_Msk     0xF00UL
#define FLASHC_FM_CTL_ANA_CTL1_PDAC_STEP_Pos    12UL
#define FLASHC_FM_CTL_ANA_CTL1_PDAC_STEP_Msk    0xF000UL
#define FLASHC_FM_CTL_ANA_CTL1_NPDAC_STEP_TIME_Pos 16UL
#define FLASHC_FM_CTL_ANA_CTL1_NPDAC_STEP_TIME_Msk 0xFF0000UL
#define FLASHC_FM_CTL_ANA_CTL1_NPDAC_ZERO_TIME_Pos 24UL
#define FLASHC_FM_CTL_ANA_CTL1_NPDAC_ZERO_TIME_Msk 0xFF000000UL
/* FLASHC_FM_CTL.FM_PL_WRDATA_ALL */
#define FLASHC_FM_CTL_FM_PL_WRDATA_ALL_DATA32_Pos 0UL
#define FLASHC_FM_CTL_FM_PL_WRDATA_ALL_DATA32_Msk 0xFFFFFFFFUL
/* FLASHC_FM_CTL.FM_REFRESH_ADDR */
#define FLASHC_FM_CTL_FM_REFRESH_ADDR_FM_BXA_Pos 0UL
#define FLASHC_FM_CTL_FM_REFRESH_ADDR_FM_BXA_Msk 0x1UL
#define FLASHC_FM_CTL_FM_REFRESH_ADDR_FM_CXA_Pos 4UL
#define FLASHC_FM_CTL_FM_REFRESH_ADDR_FM_CXA_Msk 0x10UL
/* FLASHC_FM_CTL.RGRANT_DELAY_ERS */
#define FLASHC_FM_CTL_RGRANT_DELAY_ERS_RGRANT_DELAY_ERS_SEQ01_Pos 0UL
#define FLASHC_FM_CTL_RGRANT_DELAY_ERS_RGRANT_DELAY_ERS_SEQ01_Msk 0xFFUL
#define FLASHC_FM_CTL_RGRANT_DELAY_ERS_RGRANT_DELAY_ERS_SEQ12_Pos 8UL
#define FLASHC_FM_CTL_RGRANT_DELAY_ERS_RGRANT_DELAY_ERS_SEQ12_Msk 0xFF00UL
#define FLASHC_FM_CTL_RGRANT_DELAY_ERS_RGRANT_DELAY_ERS_SEQ23_Pos 16UL
#define FLASHC_FM_CTL_RGRANT_DELAY_ERS_RGRANT_DELAY_ERS_SEQ23_Msk 0xFF0000UL
/* FLASHC_FM_CTL.RGRANT_SCALE_ERS */
#define FLASHC_FM_CTL_RGRANT_SCALE_ERS_SCALE_ERS_SEQ01_Pos 0UL
#define FLASHC_FM_CTL_RGRANT_SCALE_ERS_SCALE_ERS_SEQ01_Msk 0x3UL
#define FLASHC_FM_CTL_RGRANT_SCALE_ERS_SCALE_ERS_SEQ12_Pos 2UL
#define FLASHC_FM_CTL_RGRANT_SCALE_ERS_SCALE_ERS_SEQ12_Msk 0xCUL
#define FLASHC_FM_CTL_RGRANT_SCALE_ERS_SCALE_ERS_SEQ23_Pos 4UL
#define FLASHC_FM_CTL_RGRANT_SCALE_ERS_SCALE_ERS_SEQ23_Msk 0x30UL
#define FLASHC_FM_CTL_RGRANT_SCALE_ERS_SCALE_ERS_PEON_Pos 6UL
#define FLASHC_FM_CTL_RGRANT_SCALE_ERS_SCALE_ERS_PEON_Msk 0xC0UL
#define FLASHC_FM_CTL_RGRANT_SCALE_ERS_SCALE_ERS_PEOFF_Pos 8UL
#define FLASHC_FM_CTL_RGRANT_SCALE_ERS_SCALE_ERS_PEOFF_Msk 0x300UL
#define FLASHC_FM_CTL_RGRANT_SCALE_ERS_RGRANT_DELAY_ERS_PEON_Pos 16UL
#define FLASHC_FM_CTL_RGRANT_SCALE_ERS_RGRANT_DELAY_ERS_PEON_Msk 0xFF0000UL
#define FLASHC_FM_CTL_RGRANT_SCALE_ERS_RGRANT_DELAY_ERS_PEOFF_Pos 24UL
#define FLASHC_FM_CTL_RGRANT_SCALE_ERS_RGRANT_DELAY_ERS_PEOFF_Msk 0xFF000000UL
/* FLASHC_FM_CTL.PW_SEQ23 */
#define FLASHC_FM_CTL_PW_SEQ23_PW_SEQ2_POST_Pos 0UL
#define FLASHC_FM_CTL_PW_SEQ23_PW_SEQ2_POST_Msk 0xFFFFUL
#define FLASHC_FM_CTL_PW_SEQ23_PW_SEQ3_Pos      16UL
#define FLASHC_FM_CTL_PW_SEQ23_PW_SEQ3_Msk      0xFFFF0000UL
/* FLASHC_FM_CTL.PW_SEQ12 */
#define FLASHC_FM_CTL_PW_SEQ12_PW_SEQ1_Pos      0UL
#define FLASHC_FM_CTL_PW_SEQ12_PW_SEQ1_Msk      0xFFFFUL
#define FLASHC_FM_CTL_PW_SEQ12_PW_SEQ2_PRE_Pos  16UL
#define FLASHC_FM_CTL_PW_SEQ12_PW_SEQ2_PRE_Msk  0xFFFF0000UL
/* FLASHC_FM_CTL.WAIT_CTL */
#define FLASHC_FM_CTL_WAIT_CTL_WAIT_FM_MEM_RD_Pos 0UL
#define FLASHC_FM_CTL_WAIT_CTL_WAIT_FM_MEM_RD_Msk 0xFUL
#define FLASHC_FM_CTL_WAIT_CTL_WAIT_FM_HV_RD_Pos 8UL
#define FLASHC_FM_CTL_WAIT_CTL_WAIT_FM_HV_RD_Msk 0xF00UL
#define FLASHC_FM_CTL_WAIT_CTL_WAIT_FM_HV_WR_Pos 16UL
#define FLASHC_FM_CTL_WAIT_CTL_WAIT_FM_HV_WR_Msk 0x70000UL
#define FLASHC_FM_CTL_WAIT_CTL_FM_RWW_MODE_Pos  24UL
#define FLASHC_FM_CTL_WAIT_CTL_FM_RWW_MODE_Msk  0x3000000UL
#define FLASHC_FM_CTL_WAIT_CTL_LV_SPARE_1_Pos   26UL
#define FLASHC_FM_CTL_WAIT_CTL_LV_SPARE_1_Msk   0x4000000UL
#define FLASHC_FM_CTL_WAIT_CTL_PL_SOFT_SET_EN_Pos 29UL
#define FLASHC_FM_CTL_WAIT_CTL_PL_SOFT_SET_EN_Msk 0x20000000UL
/* FLASHC_FM_CTL.RGRANT_DELAY_PRG */
#define FLASHC_FM_CTL_RGRANT_DELAY_PRG_RGRANT_DELAY_PRG_SEQ12_Pos 0UL
#define FLASHC_FM_CTL_RGRANT_DELAY_PRG_RGRANT_DELAY_PRG_SEQ12_Msk 0xFFUL
#define FLASHC_FM_CTL_RGRANT_DELAY_PRG_RGRANT_DELAY_PRG_SEQ23_Pos 8UL
#define FLASHC_FM_CTL_RGRANT_DELAY_PRG_RGRANT_DELAY_PRG_SEQ23_Msk 0xFF00UL
#define FLASHC_FM_CTL_RGRANT_DELAY_PRG_RGRANT_DELAY_SEQ30_Pos 16UL
#define FLASHC_FM_CTL_RGRANT_DELAY_PRG_RGRANT_DELAY_SEQ30_Msk 0xFF0000UL
#define FLASHC_FM_CTL_RGRANT_DELAY_PRG_RGRANT_DELAY_CLK_Pos 24UL
#define FLASHC_FM_CTL_RGRANT_DELAY_PRG_RGRANT_DELAY_CLK_Msk 0xF000000UL
#define FLASHC_FM_CTL_RGRANT_DELAY_PRG_HV_PARAMS_LOADED_Pos 31UL
#define FLASHC_FM_CTL_RGRANT_DELAY_PRG_HV_PARAMS_LOADED_Msk 0x80000000UL
/* FLASHC_FM_CTL.TIMER_CLK_CTL */
#define FLASHC_FM_CTL_TIMER_CLK_CTL_TIMER_CLOCK_FREQ_Pos 0UL
#define FLASHC_FM_CTL_TIMER_CLK_CTL_TIMER_CLOCK_FREQ_Msk 0xFFUL
#define FLASHC_FM_CTL_TIMER_CLK_CTL_RGRANT_DELAY_PRG_PEON_Pos 8UL
#define FLASHC_FM_CTL_TIMER_CLK_CTL_RGRANT_DELAY_PRG_PEON_Msk 0xFF00UL
#define FLASHC_FM_CTL_TIMER_CLK_CTL_RGRANT_DELAY_PRG_PEOFF_Pos 16UL
#define FLASHC_FM_CTL_TIMER_CLK_CTL_RGRANT_DELAY_PRG_PEOFF_Msk 0xFF0000UL
#define FLASHC_FM_CTL_TIMER_CLK_CTL_RGRANT_DELAY_PRG_SEQ01_Pos 24UL
#define FLASHC_FM_CTL_TIMER_CLK_CTL_RGRANT_DELAY_PRG_SEQ01_Msk 0xFF000000UL
/* FLASHC_FM_CTL.TIMER_CTL */
#define FLASHC_FM_CTL_TIMER_CTL_PERIOD_Pos      0UL
#define FLASHC_FM_CTL_TIMER_CTL_PERIOD_Msk      0x7FFFUL
#define FLASHC_FM_CTL_TIMER_CTL_SCALE_Pos       15UL
#define FLASHC_FM_CTL_TIMER_CTL_SCALE_Msk       0x8000UL
#define FLASHC_FM_CTL_TIMER_CTL_AUTO_SEQUENCE_Pos 24UL
#define FLASHC_FM_CTL_TIMER_CTL_AUTO_SEQUENCE_Msk 0x1000000UL
#define FLASHC_FM_CTL_TIMER_CTL_PRE_PROG_Pos    25UL
#define FLASHC_FM_CTL_TIMER_CTL_PRE_PROG_Msk    0x2000000UL
#define FLASHC_FM_CTL_TIMER_CTL_PRE_PROG_CSL_Pos 26UL
#define FLASHC_FM_CTL_TIMER_CTL_PRE_PROG_CSL_Msk 0x4000000UL
#define FLASHC_FM_CTL_TIMER_CTL_PUMP_EN_Pos     29UL
#define FLASHC_FM_CTL_TIMER_CTL_PUMP_EN_Msk     0x20000000UL
#define FLASHC_FM_CTL_TIMER_CTL_ACLK_EN_Pos     30UL
#define FLASHC_FM_CTL_TIMER_CTL_ACLK_EN_Msk     0x40000000UL
#define FLASHC_FM_CTL_TIMER_CTL_TIMER_EN_Pos    31UL
#define FLASHC_FM_CTL_TIMER_CTL_TIMER_EN_Msk    0x80000000UL
/* FLASHC_FM_CTL.ACLK_CTL */
#define FLASHC_FM_CTL_ACLK_CTL_ACLK_GEN_Pos     0UL
#define FLASHC_FM_CTL_ACLK_CTL_ACLK_GEN_Msk     0x1UL
/* FLASHC_FM_CTL.INTR */
#define FLASHC_FM_CTL_INTR_TIMER_EXPIRED_Pos    0UL
#define FLASHC_FM_CTL_INTR_TIMER_EXPIRED_Msk    0x1UL
/* FLASHC_FM_CTL.INTR_SET */
#define FLASHC_FM_CTL_INTR_SET_TIMER_EXPIRED_Pos 0UL
#define FLASHC_FM_CTL_INTR_SET_TIMER_EXPIRED_Msk 0x1UL
/* FLASHC_FM_CTL.INTR_MASK */
#define FLASHC_FM_CTL_INTR_MASK_TIMER_EXPIRED_Pos 0UL
#define FLASHC_FM_CTL_INTR_MASK_TIMER_EXPIRED_Msk 0x1UL
/* FLASHC_FM_CTL.INTR_MASKED */
#define FLASHC_FM_CTL_INTR_MASKED_TIMER_EXPIRED_Pos 0UL
#define FLASHC_FM_CTL_INTR_MASKED_TIMER_EXPIRED_Msk 0x1UL
/* FLASHC_FM_CTL.CAL_CTL0 */
#define FLASHC_FM_CTL_CAL_CTL0_VCT_TRIM_HV_Pos  0UL
#define FLASHC_FM_CTL_CAL_CTL0_VCT_TRIM_HV_Msk  0x1FUL
#define FLASHC_FM_CTL_CAL_CTL0_CDAC_HV_Pos      5UL
#define FLASHC_FM_CTL_CAL_CTL0_CDAC_HV_Msk      0xE0UL
#define FLASHC_FM_CTL_CAL_CTL0_VBG_TRIM_HV_Pos  8UL
#define FLASHC_FM_CTL_CAL_CTL0_VBG_TRIM_HV_Msk  0x3F00UL
#define FLASHC_FM_CTL_CAL_CTL0_VBG_TC_TRIM_HV_Pos 14UL
#define FLASHC_FM_CTL_CAL_CTL0_VBG_TC_TRIM_HV_Msk 0x3C000UL
#define FLASHC_FM_CTL_CAL_CTL0_IPREF_TRIMA_HV_Pos 18UL
#define FLASHC_FM_CTL_CAL_CTL0_IPREF_TRIMA_HV_Msk 0x40000UL
#define FLASHC_FM_CTL_CAL_CTL0_SPARE_CTL0_HV_Pos 19UL
#define FLASHC_FM_CTL_CAL_CTL0_SPARE_CTL0_HV_Msk 0x80000UL
/* FLASHC_FM_CTL.CAL_CTL1 */
#define FLASHC_FM_CTL_CAL_CTL1_ICREF_TRIM_HV_Pos 0UL
#define FLASHC_FM_CTL_CAL_CTL1_ICREF_TRIM_HV_Msk 0x3FUL
#define FLASHC_FM_CTL_CAL_CTL1_ICREF_TC_TRIM_HV_Pos 6UL
#define FLASHC_FM_CTL_CAL_CTL1_ICREF_TC_TRIM_HV_Msk 0x3C0UL
#define FLASHC_FM_CTL_CAL_CTL1_IPREF_TRIM_HV_Pos 10UL
#define FLASHC_FM_CTL_CAL_CTL1_IPREF_TRIM_HV_Msk 0x7C00UL
#define FLASHC_FM_CTL_CAL_CTL1_IPREF_TC_HV_Pos  15UL
#define FLASHC_FM_CTL_CAL_CTL1_IPREF_TC_HV_Msk  0x78000UL
#define FLASHC_FM_CTL_CAL_CTL1_SPARE_CTL1_HV_Pos 19UL
#define FLASHC_FM_CTL_CAL_CTL1_SPARE_CTL1_HV_Msk 0x80000UL
/* FLASHC_FM_CTL.CAL_CTL2 */
#define FLASHC_FM_CTL_CAL_CTL2_IDAC_ULP_HV_Pos  0UL
#define FLASHC_FM_CTL_CAL_CTL2_IDAC_ULP_HV_Msk  0xFFUL
#define FLASHC_FM_CTL_CAL_CTL2_SPARE_ULP_CTL2_HV_Pos 8UL
#define FLASHC_FM_CTL_CAL_CTL2_SPARE_ULP_CTL2_HV_Msk 0x100UL
#define FLASHC_FM_CTL_CAL_CTL2_VREF_SEL_ULP_HV_Pos 9UL
#define FLASHC_FM_CTL_CAL_CTL2_VREF_SEL_ULP_HV_Msk 0x200UL
#define FLASHC_FM_CTL_CAL_CTL2_IDAC_LP_HV_Pos   10UL
#define FLASHC_FM_CTL_CAL_CTL2_IDAC_LP_HV_Msk   0x3FC00UL
#define FLASHC_FM_CTL_CAL_CTL2_SPARE_LP_CTL2_HV_Pos 18UL
#define FLASHC_FM_CTL_CAL_CTL2_SPARE_LP_CTL2_HV_Msk 0x40000UL
#define FLASHC_FM_CTL_CAL_CTL2_VREF_SEL_LP_HV_Pos 19UL
#define FLASHC_FM_CTL_CAL_CTL2_VREF_SEL_LP_HV_Msk 0x80000UL
/* FLASHC_FM_CTL.CAL_CTL3 */
#define FLASHC_FM_CTL_CAL_CTL3_OSC_TRIM_HV_Pos  0UL
#define FLASHC_FM_CTL_CAL_CTL3_OSC_TRIM_HV_Msk  0xFUL
#define FLASHC_FM_CTL_CAL_CTL3_OSC_RANGE_TRIM_HV_Pos 4UL
#define FLASHC_FM_CTL_CAL_CTL3_OSC_RANGE_TRIM_HV_Msk 0x10UL
#define FLASHC_FM_CTL_CAL_CTL3_VPROT_ACT_HV_Pos 5UL
#define FLASHC_FM_CTL_CAL_CTL3_VPROT_ACT_HV_Msk 0x20UL
#define FLASHC_FM_CTL_CAL_CTL3_OSC_TEMPCO_HV_Pos 6UL
#define FLASHC_FM_CTL_CAL_CTL3_OSC_TEMPCO_HV_Msk 0x40UL
#define FLASHC_FM_CTL_CAL_CTL3_LAT_DIS3_HV_Pos  7UL
#define FLASHC_FM_CTL_CAL_CTL3_LAT_DIS3_HV_Msk  0x80UL
#define FLASHC_FM_CTL_CAL_CTL3_PM_EN_HV_Pos     8UL
#define FLASHC_FM_CTL_CAL_CTL3_PM_EN_HV_Msk     0x100UL
#define FLASHC_FM_CTL_CAL_CTL3_REG_ACT_HV_Pos   9UL
#define FLASHC_FM_CTL_CAL_CTL3_REG_ACT_HV_Msk   0x200UL
#define FLASHC_FM_CTL_CAL_CTL3_FDIV_TRIM_HV_Pos 10UL
#define FLASHC_FM_CTL_CAL_CTL3_FDIV_TRIM_HV_Msk 0xC00UL
#define FLASHC_FM_CTL_CAL_CTL3_VDDHI_HV_Pos     12UL
#define FLASHC_FM_CTL_CAL_CTL3_VDDHI_HV_Msk     0x1000UL
#define FLASHC_FM_CTL_CAL_CTL3_TURBO_PULSEW_HV_Pos 13UL
#define FLASHC_FM_CTL_CAL_CTL3_TURBO_PULSEW_HV_Msk 0x6000UL
#define FLASHC_FM_CTL_CAL_CTL3_IOSC_TRIM_HV_Pos 15UL
#define FLASHC_FM_CTL_CAL_CTL3_IOSC_TRIM_HV_Msk 0x18000UL
#define FLASHC_FM_CTL_CAL_CTL3_CL_ISO_DIS_HV_Pos 17UL
#define FLASHC_FM_CTL_CAL_CTL3_CL_ISO_DIS_HV_Msk 0x20000UL
#define FLASHC_FM_CTL_CAL_CTL3_R_GRANT_EN_HV_Pos 18UL
#define FLASHC_FM_CTL_CAL_CTL3_R_GRANT_EN_HV_Msk 0x40000UL
#define FLASHC_FM_CTL_CAL_CTL3_LP_ULP_SW_HV_Pos 19UL
#define FLASHC_FM_CTL_CAL_CTL3_LP_ULP_SW_HV_Msk 0x80000UL
/* FLASHC_FM_CTL.CAL_CTL4 */
#define FLASHC_FM_CTL_CAL_CTL4_VLIM_TRIM_ULP_HV_Pos 0UL
#define FLASHC_FM_CTL_CAL_CTL4_VLIM_TRIM_ULP_HV_Msk 0x3UL
#define FLASHC_FM_CTL_CAL_CTL4_SPARE_CTL4_ULP_HV_Pos 2UL
#define FLASHC_FM_CTL_CAL_CTL4_SPARE_CTL4_ULP_HV_Msk 0x1CUL
#define FLASHC_FM_CTL_CAL_CTL4_SDAC_ULP_HV_Pos  5UL
#define FLASHC_FM_CTL_CAL_CTL4_SDAC_ULP_HV_Msk  0x60UL
#define FLASHC_FM_CTL_CAL_CTL4_ITIM_ULP_HV_Pos  7UL
#define FLASHC_FM_CTL_CAL_CTL4_ITIM_ULP_HV_Msk  0x1F80UL
#define FLASHC_FM_CTL_CAL_CTL4_FM_READY_DEL_ULP_HV_Pos 13UL
#define FLASHC_FM_CTL_CAL_CTL4_FM_READY_DEL_ULP_HV_Msk 0x6000UL
#define FLASHC_FM_CTL_CAL_CTL4_SA_CTL_TRIM_T8_ULP_HV_Pos 15UL
#define FLASHC_FM_CTL_CAL_CTL4_SA_CTL_TRIM_T8_ULP_HV_Msk 0x8000UL
#define FLASHC_FM_CTL_CAL_CTL4_READY_RESTART_N_HV_Pos 16UL
#define FLASHC_FM_CTL_CAL_CTL4_READY_RESTART_N_HV_Msk 0x10000UL
#define FLASHC_FM_CTL_CAL_CTL4_VBST_S_DIS_HV_Pos 17UL
#define FLASHC_FM_CTL_CAL_CTL4_VBST_S_DIS_HV_Msk 0x20000UL
#define FLASHC_FM_CTL_CAL_CTL4_AUTO_HVPULSE_HV_Pos 18UL
#define FLASHC_FM_CTL_CAL_CTL4_AUTO_HVPULSE_HV_Msk 0x40000UL
#define FLASHC_FM_CTL_CAL_CTL4_UGB_EN_HV_Pos    19UL
#define FLASHC_FM_CTL_CAL_CTL4_UGB_EN_HV_Msk    0x80000UL
/* FLASHC_FM_CTL.CAL_CTL5 */
#define FLASHC_FM_CTL_CAL_CTL5_VLIM_TRIM_LP_HV_Pos 0UL
#define FLASHC_FM_CTL_CAL_CTL5_VLIM_TRIM_LP_HV_Msk 0x3UL
#define FLASHC_FM_CTL_CAL_CTL5_SPARE_CTL5_LP_HV_Pos 2UL
#define FLASHC_FM_CTL_CAL_CTL5_SPARE_CTL5_LP_HV_Msk 0x1CUL
#define FLASHC_FM_CTL_CAL_CTL5_SDAC_LP_HV_Pos   5UL
#define FLASHC_FM_CTL_CAL_CTL5_SDAC_LP_HV_Msk   0x60UL
#define FLASHC_FM_CTL_CAL_CTL5_ITIM_LP_HV_Pos   7UL
#define FLASHC_FM_CTL_CAL_CTL5_ITIM_LP_HV_Msk   0x1F80UL
#define FLASHC_FM_CTL_CAL_CTL5_FM_READY_DEL_LP_HV_Pos 13UL
#define FLASHC_FM_CTL_CAL_CTL5_FM_READY_DEL_LP_HV_Msk 0x6000UL
#define FLASHC_FM_CTL_CAL_CTL5_SA_CTL_TRIM_T8_LP_HV_Pos 15UL
#define FLASHC_FM_CTL_CAL_CTL5_SA_CTL_TRIM_T8_LP_HV_Msk 0x8000UL
#define FLASHC_FM_CTL_CAL_CTL5_SPARE2_CTL5_LP_HV_Pos 16UL
#define FLASHC_FM_CTL_CAL_CTL5_SPARE2_CTL5_LP_HV_Msk 0x30000UL
#define FLASHC_FM_CTL_CAL_CTL5_AMUX_SEL_HV_Pos  18UL
#define FLASHC_FM_CTL_CAL_CTL5_AMUX_SEL_HV_Msk  0xC0000UL
/* FLASHC_FM_CTL.CAL_CTL6 */
#define FLASHC_FM_CTL_CAL_CTL6_SA_CTL_TRIM_T1_ULP_HV_Pos 0UL
#define FLASHC_FM_CTL_CAL_CTL6_SA_CTL_TRIM_T1_ULP_HV_Msk 0x3UL
#define FLASHC_FM_CTL_CAL_CTL6_SA_CTL_TRIM_T4_ULP_HV_Pos 2UL
#define FLASHC_FM_CTL_CAL_CTL6_SA_CTL_TRIM_T4_ULP_HV_Msk 0x1CUL
#define FLASHC_FM_CTL_CAL_CTL6_SA_CTL_TRIM_T5_ULP_HV_Pos 5UL
#define FLASHC_FM_CTL_CAL_CTL6_SA_CTL_TRIM_T5_ULP_HV_Msk 0xE0UL
#define FLASHC_FM_CTL_CAL_CTL6_SA_CTL_TRIM_T6_ULP_HV_Pos 8UL
#define FLASHC_FM_CTL_CAL_CTL6_SA_CTL_TRIM_T6_ULP_HV_Msk 0x300UL
#define FLASHC_FM_CTL_CAL_CTL6_SA_CTL_TRIM_T1_LP_HV_Pos 10UL
#define FLASHC_FM_CTL_CAL_CTL6_SA_CTL_TRIM_T1_LP_HV_Msk 0xC00UL
#define FLASHC_FM_CTL_CAL_CTL6_SA_CTL_TRIM_T4_LP_HV_Pos 12UL
#define FLASHC_FM_CTL_CAL_CTL6_SA_CTL_TRIM_T4_LP_HV_Msk 0x7000UL
#define FLASHC_FM_CTL_CAL_CTL6_SA_CTL_TRIM_T5_LP_HV_Pos 15UL
#define FLASHC_FM_CTL_CAL_CTL6_SA_CTL_TRIM_T5_LP_HV_Msk 0x38000UL
#define FLASHC_FM_CTL_CAL_CTL6_SA_CTL_TRIM_T6_LP_HV_Pos 18UL
#define FLASHC_FM_CTL_CAL_CTL6_SA_CTL_TRIM_T6_LP_HV_Msk 0xC0000UL
/* FLASHC_FM_CTL.CAL_CTL7 */
#define FLASHC_FM_CTL_CAL_CTL7_ERSX8_CLK_SEL_HV_Pos 0UL
#define FLASHC_FM_CTL_CAL_CTL7_ERSX8_CLK_SEL_HV_Msk 0x3UL
#define FLASHC_FM_CTL_CAL_CTL7_FM_ACTIVE_HV_Pos 2UL
#define FLASHC_FM_CTL_CAL_CTL7_FM_ACTIVE_HV_Msk 0x4UL
#define FLASHC_FM_CTL_CAL_CTL7_TURBO_EXT_HV_Pos 3UL
#define FLASHC_FM_CTL_CAL_CTL7_TURBO_EXT_HV_Msk 0x8UL
#define FLASHC_FM_CTL_CAL_CTL7_NPDAC_HWCTL_DIS_HV_Pos 4UL
#define FLASHC_FM_CTL_CAL_CTL7_NPDAC_HWCTL_DIS_HV_Msk 0x10UL
#define FLASHC_FM_CTL_CAL_CTL7_FM_READY_DIS_HV_Pos 5UL
#define FLASHC_FM_CTL_CAL_CTL7_FM_READY_DIS_HV_Msk 0x20UL
#define FLASHC_FM_CTL_CAL_CTL7_ERSX8_EN_ALL_HV_Pos 6UL
#define FLASHC_FM_CTL_CAL_CTL7_ERSX8_EN_ALL_HV_Msk 0x40UL
#define FLASHC_FM_CTL_CAL_CTL7_READY_DEL_HV_Pos 7UL
#define FLASHC_FM_CTL_CAL_CTL7_READY_DEL_HV_Msk 0x80UL
#define FLASHC_FM_CTL_CAL_CTL7_SPARE_CTL7_HV_Pos 8UL
#define FLASHC_FM_CTL_CAL_CTL7_SPARE_CTL7_HV_Msk 0x300UL
#define FLASHC_FM_CTL_CAL_CTL7_PTRIM_ULP_HV_Pos 10UL
#define FLASHC_FM_CTL_CAL_CTL7_PTRIM_ULP_HV_Msk 0xC00UL
#define FLASHC_FM_CTL_CAL_CTL7_SPARE2_CTL7_ULP_HV_Pos 12UL
#define FLASHC_FM_CTL_CAL_CTL7_SPARE2_CTL7_ULP_HV_Msk 0x7000UL
#define FLASHC_FM_CTL_CAL_CTL7_PTRIM_LP_HV_Pos  15UL
#define FLASHC_FM_CTL_CAL_CTL7_PTRIM_LP_HV_Msk  0x18000UL
#define FLASHC_FM_CTL_CAL_CTL7_SPARE3_CTL7_LP_HV_Pos 17UL
#define FLASHC_FM_CTL_CAL_CTL7_SPARE3_CTL7_LP_HV_Msk 0xE0000UL
/* FLASHC_FM_CTL.FM_PL_ECC */
#define FLASHC_FM_CTL_FM_PL_ECC_DATA9_Pos       0UL
#define FLASHC_FM_CTL_FM_PL_ECC_DATA9_Msk       0x1FFUL
#define FLASHC_FM_CTL_FM_PL_ECC_DATA9_1_Pos     16UL
#define FLASHC_FM_CTL_FM_PL_ECC_DATA9_1_Msk     0x1FF0000UL
/* FLASHC_FM_CTL.FM_MEM_DATA */
#define FLASHC_FM_CTL_FM_MEM_DATA_DATA32_Pos    0UL
#define FLASHC_FM_CTL_FM_MEM_DATA_DATA32_Msk    0xFFFFFFFFUL
/* FLASHC_FM_CTL.FM_MEM_ECC */
#define FLASHC_FM_CTL_FM_MEM_ECC_ECC_PARITY_Pos 0UL
#define FLASHC_FM_CTL_FM_MEM_ECC_ECC_PARITY_Msk 0x1FFUL
/* FLASHC_FM_CTL.FM_ECC_CTL_ADDR */
#define FLASHC_FM_CTL_FM_ECC_CTL_ADDR_ECC_CTL_ADDR_Pos 0UL
#define FLASHC_FM_CTL_FM_ECC_CTL_ADDR_ECC_CTL_ADDR_Msk 0x1UL
/* FLASHC_FM_CTL.FM_RED_CTL_SM01_ADDR */
#define FLASHC_FM_CTL_FM_RED_CTL_SM01_ADDR_FM_RED_CTL_SM01_ADDR_Pos 0UL
#define FLASHC_FM_CTL_FM_RED_CTL_SM01_ADDR_FM_RED_CTL_SM01_ADDR_Msk 0xFFFFFFFFUL
/* FLASHC_FM_CTL.FM_RED_CTL67_ADDR */
#define FLASHC_FM_CTL_FM_RED_CTL67_ADDR_FM_RED_CTL67_ADDR_Pos 0UL
#define FLASHC_FM_CTL_FM_RED_CTL67_ADDR_FM_RED_CTL67_ADDR_Msk 0xFFFFFFFFUL
/* FLASHC_FM_CTL.FM_RED_CTL45_ADDR */
#define FLASHC_FM_CTL_FM_RED_CTL45_ADDR_FM_RED_CTL45_ADDR_Pos 0UL
#define FLASHC_FM_CTL_FM_RED_CTL45_ADDR_FM_RED_CTL45_ADDR_Msk 0xFFFFFFFFUL
/* FLASHC_FM_CTL.FM_CAL_CTL8_ADDR */
#define FLASHC_FM_CTL_FM_CAL_CTL8_ADDR_FM_CAL_CTL8_ADDR_Pos 0UL
#define FLASHC_FM_CTL_FM_CAL_CTL8_ADDR_FM_CAL_CTL8_ADDR_Msk 0xFFFFFFFFUL


/* FLASHC.FLASH_CTL */
#define FLASHC_FLASH_CTL_RBUS_WS_Pos            0UL
#define FLASHC_FLASH_CTL_RBUS_WS_Msk            0xFUL
#define FLASHC_FLASH_CTL_BANK_MAPPING_Pos       8UL
#define FLASHC_FLASH_CTL_BANK_MAPPING_Msk       0x300UL
#define FLASHC_FLASH_CTL_BANK_MODE_Pos          12UL
#define FLASHC_FLASH_CTL_BANK_MODE_Msk          0x1000UL
#define FLASHC_FLASH_CTL_ECC_EN_Pos             16UL
#define FLASHC_FLASH_CTL_ECC_EN_Msk             0x10000UL
#define FLASHC_FLASH_CTL_RBUS_ERR_SILENT_Pos    18UL
#define FLASHC_FLASH_CTL_RBUS_ERR_SILENT_Msk    0x40000UL
#define FLASHC_FLASH_CTL_ENFORCE_PC_LOCK_Pos    24UL
#define FLASHC_FLASH_CTL_ENFORCE_PC_LOCK_Msk    0x1000000UL
#define FLASHC_FLASH_CTL_BLOCK_SECTOR_OPERATIONS_Pos 25UL
#define FLASHC_FLASH_CTL_BLOCK_SECTOR_OPERATIONS_Msk 0x2000000UL
#define FLASHC_FLASH_CTL_BLOCK_SUBSECTOR_OPERATIONS_Pos 26UL
#define FLASHC_FLASH_CTL_BLOCK_SUBSECTOR_OPERATIONS_Msk 0x4000000UL
#define FLASHC_FLASH_CTL_BLOCK_BULK_OPERATIONS_Pos 27UL
#define FLASHC_FLASH_CTL_BLOCK_BULK_OPERATIONS_Msk 0x8000000UL
/* FLASHC.FLASH_SECTOR_M */
#define FLASHC_FLASH_SECTOR_M_SECTOR_M_Pos      0UL
#define FLASHC_FLASH_SECTOR_M_SECTOR_M_Msk      0xFFFFFFFFUL
/* FLASHC.FLASH_MAIN_N */
#define FLASHC_FLASH_MAIN_N_MAIN_N_Pos          0UL
#define FLASHC_FLASH_MAIN_N_MAIN_N_Msk          0xFFFFFFFFUL
/* FLASHC.FLASH_WORK_Z */
#define FLASHC_FLASH_WORK_Z_WORK_Z_Pos          0UL
#define FLASHC_FLASH_WORK_Z_WORK_Z_Msk          0xFFFFFFFFUL
/* FLASHC.FLASH_SFLASH_Y */
#define FLASHC_FLASH_SFLASH_Y_SFLASH_Y_Pos      0UL
#define FLASHC_FLASH_SFLASH_Y_SFLASH_Y_Msk      0xFFUL
#define FLASHC_FLASH_SFLASH_Y_SFLASH_SECNUM_Pos 31UL
#define FLASHC_FLASH_SFLASH_Y_SFLASH_SECNUM_Msk 0x80000000UL
/* FLASHC.FLASH_REFRESH_ROW */
#define FLASHC_FLASH_REFRESH_ROW_REFRESH_ROW_Pos 0UL
#define FLASHC_FLASH_REFRESH_ROW_REFRESH_ROW_Msk 0xFFFFFFFFUL
/* FLASHC.FLASH_CMD */
#define FLASHC_FLASH_CMD_BUFF_INV_Pos           1UL
#define FLASHC_FLASH_CMD_BUFF_INV_Msk           0x2UL
/* FLASHC.FLASH_LOCK */
#define FLASHC_FLASH_LOCK_PC_Pos                0UL
#define FLASHC_FLASH_LOCK_PC_Msk                0xFUL
#define FLASHC_FLASH_LOCK_LOCKED_Pos            31UL
#define FLASHC_FLASH_LOCK_LOCKED_Msk            0x80000000UL
/* FLASHC.FLASH_PWR_CTL */
#define FLASHC_FLASH_PWR_CTL_ENABLE_Pos         0UL
#define FLASHC_FLASH_PWR_CTL_ENABLE_Msk         0x1UL
#define FLASHC_FLASH_PWR_CTL_ENABLE_HV_Pos      1UL
#define FLASHC_FLASH_PWR_CTL_ENABLE_HV_Msk      0x2UL
/* FLASHC.ENFORCE_PC_LOCK_SHADOW */
#define FLASHC_ENFORCE_PC_LOCK_SHADOW_PC_LOCK_SHADOW_Pos 0UL
#define FLASHC_ENFORCE_PC_LOCK_SHADOW_PC_LOCK_SHADOW_Msk 0x1UL
/* FLASHC.ECC_INJ_EN */
#define FLASHC_ECC_INJ_EN_ECC_INJ_ENABLE_Pos    0UL
#define FLASHC_ECC_INJ_EN_ECC_INJ_ENABLE_Msk    0x1UL
#define FLASHC_ECC_INJ_EN_ECC_ERROR_Pos         8UL
#define FLASHC_ECC_INJ_EN_ECC_ERROR_Msk         0x100UL
#define FLASHC_ECC_INJ_EN_ECC_INJ_PC_Pos        28UL
#define FLASHC_ECC_INJ_EN_ECC_INJ_PC_Msk        0xF0000000UL
/* FLASHC.ECC_INJ_CTL */
#define FLASHC_ECC_INJ_CTL_WORD_ADDR_Pos        0UL
#define FLASHC_ECC_INJ_CTL_WORD_ADDR_Msk        0x7FFFFFUL
#define FLASHC_ECC_INJ_CTL_PARITY_Pos           23UL
#define FLASHC_ECC_INJ_CTL_PARITY_Msk           0xFF800000UL
/* FLASHC.ECC_LOGIR */
#define FLASHC_ECC_LOGIR_ECCTHRESHOLD_Pos       0UL
#define FLASHC_ECC_LOGIR_ECCTHRESHOLD_Msk       0xFFFFUL
#define FLASHC_ECC_LOGIR_ECC1CNT_Pos            16UL
#define FLASHC_ECC_LOGIR_ECC1CNT_Msk            0xFFFF0000UL


#endif /* _CYIP_FLASHC_H_ */


/* [] END OF FILE */
